This invention relates to a semiconductor memory device having associative memory cell arrays, and particularly relates to a semiconductor memory device suitable for high-speed address translation.
A virtual storage has been known as one of memory management configurations in a 32-bit microprocessor and the like. In the virtual storage, a logical address space (virtual address space) is required to correspond to a physical address space (real address space). For making the correspondence, a paging method is chiefly adopted. According to the paging method, the logical address space and the physical address space are respectively divided into set sized pages to determine the correspondence between the page number of the logical address space and that of the physical address space. For instance, in case where a logical address space to be accessed with a 32-bit logical address (VA[31:0]) is divided into 4 KB (kilobyte) sized pages, the upper 20 bits (VA[31:12]) of the logical address are dealt with as an index indicating the page number of the logical address space, and the lower 12 bits (VA[11:0]) are regarded as a relative address in the page, i.e., a displacement. The page number (VA[31:12]) of the logical address space is translated into the page number (index) of the physical address space by an address translating device, commonly called a TLB (tranlation lookaside buffer). The physical address space are accessed by a combination of the page number of the physical address space and the displacement (VA[11:0]).
An associative memory, i.e., a CAM (content addressable memory) is incorporated in a TLB. In the TLB keys are searched in parallel, which leads to a high-spaced performance of the correspondence of page numbers. A basic structure of the conventional TLB of this type is disclosed in "A 40 MIPS (PEAK) 64-bit Microprocessor with One-Clock physical Cache Load/Store", ISSCC DIGEST OF TECHNICAL PAPERS, pp. 42-44, February 1990 by Miyake, J. et al., and the like. The TLB has a plurality of entries composed of a combination of CAM cell arrays and RAM (random access memory) cell arrays. Each CAM cell array has bit lines for supplying a logical address (index part only), one word line (CAM word line) for selecting a write entry, and one sense line for comparing operation (conformity detection). Each RAM cell array has bit lines composing a single port for read/write of a physical address (index part only), and one word line (RAM word line) for selecting read/write entries. The word line of each RAM cell array is asserted by a logical sum of a signal on the word line of the corresponding CAM cell array and a signal on the sense line thereof.
In the conventional TLB, a fixed bit length of the CAM cell array in each entry is available. While, in the paging method, the page size is desirable to be changeable. There is a case where the page size is desired to be changed according to the scale of a program. Especially, when a plurality of tasks are processed in parallel in a workstation, page sizes occasionally differ with tasks. In such a case, conventionally, it is necessary to write dummy bits into the CAM cell arrays by a software.
In a detail, in case where one of four page sizes, 4 KB, 256 KB, 16 MB (megabyte) and 4 GB (gigabyte) is to be selected, the TLB must include CAM cell arrays for the longest index to specifying a page with a minimum page size. When the 256 KB or 16 MB page size is selected, the index of a 14-bit or 8-bit length (VA[31:18] or VA[31:24] has only to be dealt with, while the lower 18 bits or the lower 24 bits (VA[17:0] or V[23:0]) of the 32-bit logical address (VA[31:01] ) are regarded as a displacement. With the 4 GB page size, the 32-bit logical address (VA[31:0] ) is entirely regarded as a displacement, and the page number of the logical address space and that of the physical address space are in a correspondence of one to one. On the other hand, with the minimum page size, 4 KB, it is required to deal with the longest index (VA[31:12]) of 20 bits. Therefore, the TLB should have CAM cell arrays each having 20 CAM cells.
In this case, when the page size is set to 4 KB, all CAM cells in each CAM cell array are effectively used. Each CAM cell array stores 20-bit index (VA[31:12]) at assertion of the CAM word line, and asserts the sense line according to a result of comparing the stored index with a 20-bit index newly given on the bit lines. As a result, a RAM cell array belonging to the same entry as a hit CAM cell array is selected, thus obtaining a desired physical address. However, when the page size is set to 256 KB, for example, the number of effectively used CAM cells are only 14 out of 20, and the dummy bits each having set value must be written into the remaining six CAM cells, because the same comparing operation is carried out in the six CAM cells as in the other CAM cells.
In the above conventional TLB, the RAM word line is asserted by a logical sum of the CAM word line and the sense line in each entry, thus a sense circuit for driving the RAM word line according to the state of the sense line is complicated. This hinders from a high-speed operation of the TLB.
Further, since the above conventional TLB is provided with a single read/write port for a physical address in each of the RAM cell arrays, it is liable to cause a malfunction of an unexpected write into the RAM cell array. The logical address (index part only) is given onto the bit lines of the CAM cell arrays at the comparing operation. When two or more CAM cell arrays store respectively logical addresses which are approximate to each other, with difference in signal delay time of each bit line, a plurality of sense lines are asserted concurrently, with a result that a plurality of the RAM cell arrays are selected. Hence, the physical address read out from a certain selected RAM cell array is written into another RAM cell array which is selected at the same time. Thus, a correct physical address in the latter RAM cell array is mis-rewritten.
Moreover, in the above conventional TLB, since the available bit length of the CAM cell array in each entry is fixed, even when one of the page sizes other than minimum page size (256 KB, 16 MB, 4 GB in the above example) is applied, the comparing operation is carried out in all CAM cells prepared for the minimum page size. Thus, the wiring of the sense line of each CAM cell array is occasionally long unnecessarily and each sense line has large wiring capacitance. This prevents a high-speed comparing operation in the CAM cell arrays, and in its turn, prevents a high-speed operation of the TLB. In addition, an electric power is unnecessarily dissipated for precharging the sense line.